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june 2006 rev 4 1/33 33 L6732 adjustable step-down controller with synchronous rectification features input voltage range from 1.8v to 14v supply voltage range from 4.5v to 14v adjustable output voltage down to 0.6v with 0.8% accuracy over line voltage and temperature (0c~125c) fixed frequency voltage mode control t on lower than 100ns 0% to 100% duty cycle external input voltage reference soft-start and inhibit high current embedded drivers predictive anti-cross conduction control programmable high-side and low-side r ds(on) sense over-current-protection selectable switching frequency 250khz/ 500khz pre-bias start up capability power good output master/slave synchronization with 180 phase shift over voltage protection thermal shut-down package: htssop16 applications lcd & pdp tv high performance / high density dc-dc modules low voltage distributed dc-dc nipol converters ddr memory supply graphic cards htssop16 (exposed pad) www.st.com order codes part number package packing L6732 htssop16 tube L6732tr htssop16 tape & reel
contents L6732 2/33 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin connections and f unctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 internal ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 bypassing the ldo to avoid the voltage drop with low vcc . . . . . . . . . . . . . 12 5.4 internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.7 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.8 monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.9 hiccup mode during an ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.10 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.11 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.12 minimum on-time (ton, min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.13 bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.13.1 fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L6732 contents 3/33 6 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 L6732 demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
summary description L6732 4/33 1 summary description the controller is an integrated circuit realized in bcd5 (bicmo s-dmos, version 5) fabrication that provides complete control logic and protection for high performance step-down dc-dc and nipol converters. it is designed to drive n-cha nnel mosfets in a synchronous rectified buck topology. the output voltage of the converter can be precisely regulated down to 600mv with a maximum tolerance of 0.8% and it is also possible to use an external reference from 0v to 2.5v. the input voltage can range from 1.8v to 14v, while the supply voltage can range from 4.5v to 14v. high peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20a. the pwm duty cycle can range from 0% to 100% with a minimum on-time (t on , min ) lower than 100ns making possible conversions with very low duty cycle at high switching frequency. the device provides voltage-mode control that includes a selectable frequency osc illator (250khz or 500khz). the error amplifier features a 10mhz gain-bandwidth-product and 5v/s slew-rate that permits to realize high converter bandwidth for fast transient response. the device monitors the current by using the r ds(on) of both the high-side and low-side mosfet(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protection in all the application conditions. when necessary, two different current limit protections can be externally set through two external resistors. during the soft-start phase a constant current protection is provided while after the soft-start the device enters in hiccup mode in case of over-current. during the soft-start, the sink mode capability is disabled in order to allow a proper start-up also in pre-biased output voltage conditions. after the soft-start the device can sink current. other features are power-good, master/slave synchronization (with 180 phase shift), over-voltage-protection, feed-back disconnection and thermal shutdown. the htssop16 package allows the realization of really compact dc/dc converters.
L6732 summary description 5/33 1.1 functional description figure 1. block diagram vin=1.8v-14v vcc = 4.5 v - 1 4 v L6732 pgnd phase gnd lgate boot hgate och fb ss monitor protection and ref osc + - + - e/a pwm vccdr - + - 0.6v ocl comp earef ldo pgnd phase gnd lgate boot hgate och v out fb ss monitor protection and ref osc + - + - + - e/a pwm vccdr - + - ocl comp earef ldo pgood synch
electrical data L6732 6/33 2 electrical data 2.1 maximum rating table 1. absolute maximum ratings 2.2 thermal data table 2. thermal data symbol parameter value unit v cc v cc to gnd and pgnd, och, pgood -0.3 to 18 v v boot - v phase boot voltage 0 to 6 v v hgate - v phase 0 to v boot - v phase v v boot boot -0.3 to 24 v v phase phase -1 to 18 v phase spike, transient < 50ns (f sw = 500khz) -3 +24 ss, fb, earef, sync, ocl, lgate, comp, v ccdr -0.3 to 6 v och pin maximum withstanding voltage range test condition: cdf-aec-q100-002 "human body model" acceptance criteria: "normal performance" 1500 v pgood pin 1000 other pins 2000 symbol description value unit r thja thermal resistance junction to ambient 50 c/w t stg storage temperature range -40 to +150 c t j junction operating temperature range -40 to +125 c t a ambient operating temperature range -40 to +85 c
L6732 pin connections and functions 7/33 3 pin connections and functions figure 2. pins connection ( top view) table 3. pin functions pin n. name function 1 pgood this pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). if not used it may be left floating. pull-up this pin to v ccdr with a 10k resistor to obtain a logical signal. 2 synch it is a master-slave pin. two or more devices can be synchronized by simply connecting the synch pins together. the device operating with the highest fsw will be the master. the slave devices will operat e with 180 phase shift from the master. the best way to synchronize devices together is to set their fsw at the same value. if it is not used the synch pin can be left floating. 3 sgnd all the internal references are referred to this pin. 4 fb this pin is connected to the error amplifier inverting input. connect it to v out through the compensation network. this pin is also used to sense the output voltage in order to manage the over voltage conditions and the pgood signal. 5 comp this pin is connected to the error amplif ier output and is used to compensate the voltage control feedback loop. 6 ss/inh the soft-start time is programmed connecting an external capacitor from this pin and gnd. the internal current generator forces a current of 10 a through the capacitor. when the voltage at this pin is lower than 0.5v the device is disabled. 1 2 3 4 5 6 11 12 htssop16 13 14 15 16 sgnd earef fb pgood synch comp vcc lgate phase ss/inh pgnd 7 10 vccdr boot hgate 8 9 ocl och
pin connections and functions L6732 8/33 7 earef by setting the voltage at this pin is possibl e to select the internal/external reference and the switching frequency: v earef 0-80% of v ccdr -> external reference/f sw =250khz v earef = 80%-95% of v ccdr -> v ref = 0.6v/f sw =500khz v earef = 95%-100% of v ccdr -> v ref = 0.6v/f sw =250khz an internal clamp limits the maximum v earef at 2.5v (typ.). the device captures the analog value present at this pin at the start-up when v cc meets the uvlo threshold. 8 ocl a resistor connected from this pin to ground sets the valley- current-limit. the valley current is sensed through the low-side mo sfet(s). the internal current generator sources a current of 100a (i ocl ) from this pin to ground through the external resistor (r ocl ). the over-current threshold is given by the following equation: connecting a capacitor from this pin to gnd helps in reducing the noise injected from v cc to the device, but can be a low impedance path for the high-frequency noise related to the gnd. connect a capacitor only to a "clean" gnd. 9 och a resistor connected from this pin and th e high-side mosfet(s) drain sets the peak- current-limit. the peak current is sensed through the high-s ide mosfet(s). the internal 100a current generator (i och ) sinks a current from the drain through the external resistor (r och ). the over-current threshold is given by the following equation: 10 phase this pin is connected to the source of the high-side mosfet(s) and provides the return path for the high-side driver. this pin monitors the drop across both the upper and lower mosfet(s) for the current limit together with och and ocl. 11 hgate this pin is connected to the high-side mosfet(s) gate. 12 boot through this pin is supplied the high-side driver. connect a capacitor from this pin to the phase pin and a diode from v ccdr to this pin (cathode versus boot). 13 pgnd this pin has to be connected closely to the low-side mosfet(s) source in order to reduce the noise injection into the device. 14 lgate this pin is connected to the low-side mosfet(s) gate. 15 v ccdr 5v internally regulated voltage. it is used to supply the internal drivers. filter it to ground with at least 1f ceramic cap. 16 v cc supply voltage pin. the operative supply voltage range is from 4.5v to 14v. table 3. pin functions i valley i ocl i ocl ? 2r dsonls ? -------------------------------- - = i peak i och r och ? r dsonhs --------------------------------- =
L6732 electrical characteristics 9/33 4 electrical characteristics v cc = 12v, t a = 25c unless otherwise specified. table 4. electrical characteristics symbol parameter test condition min. typ. max. unit v cc supply current i cc v cc stand by current osc = open; ss to gnd 7 9 ma v cc quiescent current osc= open; hg = open, lg = open, ph=open 8.5 10 power-on v cc tu r n - o n v cc threshold v och = 1.7v 4.0 4.2 4.4 v tu r n - o f f v cc threshold v och = 1.7v 3.6 3.8 4.0 v v in ok tu r n - o n v och threshold 1.1 1.25 1.47 v v in ok tu r n - o f f v och threshold 0.9 1.05 1.27 v v ccdr regulation v ccdr voltage v cc =5.5v to 14v i dr = 1ma to 100ma 4.555.5v soft start and inhibit i ss soft start current ss = 2v 7 10 13 a ss = 0 to 0.5v 20 30 45 oscillator f osc accuracy 237 250 263 khz 450 500 550 khz ? v osc ramp amplitude 2.1 v output voltage v fb output voltage v dis = 0 to v th 0.597 0.6 0.603 v
L6732 electrical characteristics 10/33 table 5. thermal characteristics (v cc = 12v) symbol parameter test condition min. typ. max. unit error amplifier r earef earef input resistance vs. gnd 70 100 150 k ? i fb i.i. bias current v f = 0v 0.290 0.5 a ext ref clamp 2.3 v v offset error amplifier offset vref = 0.6v -5 +5 mv g v open loop voltage gain guaranteed by design 100 db gbwp gain-bandwidth product guaranteed by design 10 mhz sr slew-rate comp = 10pf guaranteed by design 5v/ s gate drivers r hgate_on high side source resistance v boot - v phase = 5v 1.7 ? r hgate_off high side sink resistance v boot - v phase = 5v 1.12 ? r lgate_on low side source resistance v ccdr = 5v 1.15 ? r lgate_off low side sink resistance v ccdr = 5v 0.6 ? protections i och och current source v och = 1.7v 90 100 110 ? i ocl ocl current source 90 100 110 ? ovp over voltage trip (vfb / vearef) v fb rising v earef = 0.6v 120 % v fb falling v earef = 0.6v 117 % power good och current source v och = 1.7v 90 100 110 ? ocl current source 90 100 110 ? ovp over voltage trip (vfb / vearef) v fb rising v earef = 0.6v 120 % symbol parameter test condit ion min. typ. max. unit output voltage v fb output voltage t j = 0c~ 125c 0.596 0.6 0.605 v t j = -40c~ 125c 0.593 0.6 0.605 table 4. electrical characteristics
L6732 device description 11/33 5 device description 5.1 oscillator the switching frequency can be fixed to two values: 250khz or 500khz by setting the proper voltage at the earef pin (see table 3. pins function and section 4.3 internal and external reference). 5.2 internal ldo an internal ldo supplies the internal circuitry of the device. the input of this stage is the v cc pin and the output (5v) is the v ccdr pin ( figure 3. ). the ldo can be by-passed, providing directly a 5v voltage to v ccdr . in this case v cc and v ccdr pins must be shorted together as shown in figure 4. v ccdr pin must be filtered with at least 1f capacitor to sustain the internal ldo during the recharge of the bootstrap capacitor. v ccdr also represents a voltage reference for pgood pin (see table 3. pins function). figure 3. ldo block diagram. ldo 4.5 14v
device description L6732 12/33 5.3 bypassing the ldo to avoid the voltage drop with low vcc if v cc 5v the internal ldo works in dropout with an output resistance of about 1 ? . the maximum ldo output current is about 100ma and so the output voltage drop is 100mv, to avoid this the ldo can be bypassed. 5.4 internal and external references it is possible to set the internal/external reference and the switching frequency by setting the proper voltage at the earef pin. the maximum value of the external reference depends on the v cc : with v cc = 4v the clamp operates at about 2v (typ.), while with v cc greater than 5v the maximum external reference is 2.5v (typ.). v earef from 0% to 80% of v ccdr -> external reference/fsw=250khz v earef from 80% to 95% of v ccdr -> v ref = 0.6v/fsw=500khz v earef from 95% to 100% of v ccdr -> v ref = 0.6v/fsw=250khz providing an external reference from 0v to 450mv the output voltage will be regulated but some restrictions must be considered: the minimum ovp threshold is set at 300mv; the under-voltage-protection doesn't work; the pgood signal remains low; to set the resistor divider it must be considered that a 100k pull-down resistor is integrated into the device (see figure 5. ). finally it must be taken into account that the voltage at the earef pin is captured by the device at the start-up when v cc is about 4v. figure 4. bypassing the ldo
L6732 device description 13/33 5.5 error amplifier 5.6 soft start when both v cc and v in are above their turn-on thresholds (v in is monitored by the och pin) the start-up phase takes place. otherwise the ss pin is internally shorted to gnd. at start-up, a ramp is generated charging the external capacitor c ss with an internal current generator. the initial value for this current is 35a and charges the capacitor up to 0.5v. after that it becomes 10a until the final charge value of approximately 4v (see figure 6. ). the output of the error amplifier is clamped with this voltage (v ss ) until it reaches the prog rammed value. no switching activity is observable if v ss is lower than 0.5v and both mosfets are off. when v ss is between 0.5v and 1.1v the low-side mosfet is turned on because the comp signal is lower than the valley of the triangular wave and so the duty-cycle is 0%. as v ss reaches 1.1v (i.e. the oscillator triangular wave inferior limit) even the high-side mosfet begi ns to switch and the output voltage starts to increase. the L6732 can only source current during the soft-start phase in order to manage the prebias start-up applications. this means that when the start-up occurs with output voltage greater than 0v (pre-bias startup), even when vss is between 0.5v and 1.1v the low-side mosfet is kept off (see figure 7. and figure 8. ). figure 5. error amplifier reference
device description L6732 14/33 figure 6. device start-up: voltage at the ss pin. figure 7. start-up without pre-bias v cc v in t t 0.5v 4v v cc v in v ss 4.2v 1.25v lgate v out i l v ss lgate v out i l v ss
L6732 device description 15/33 the L6732 can sink or source current after the soft-start phase (see figure 9. ). if an over current is detected during the soft-start phase, the device provides a constant-current- protection. in this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value and so, in case of high ripple current during the soft-start, the converter can start in any case, limiting the current (see section 4.6 monitoring and protections) but not entering in hiccup mode. during normal operation, if any under-voltage is detected on one of the two supplies, the ss pin is internally shorted to gnd and so the ss capacitor is rapidly discharged. figure 8. start-up with pre-bias figure 9. inductor current during and after soft-start. v ss i l v out lgate v out i l v ss v cc
device description L6732 16/33 5.7 driver section the high-side and low-side drivers allow using different types of power mosfets (also multiple mosfets to reduce the r dson ), maintaining fast switching tr ansitions. the low-side driver is supplied by v ccdr while the high-side driver is supplied by the boot pin. a predictive dead time control avoids mosfets cross-conduction maintaining very short dead time duration in the range of 20ns. the control monitors the phase node in order to sense the low-side body diode recirculation. if the phase node voltage is less than a certain threshold (-350mv typ.) during the dead time, it will be reduced in the ne xt pwm cycle. the predic tive dead time control doesn't work when the high-side body diode is conducting because the phase node doesn't go negative. this situation happens when the converte r is sinking current for example and, in this case, an adaptive dead time control operates. 5.8 monitoring and protections the output voltage is monitored by means of pin fb. if it is not within 10% (typ.) of the programmed value, the power-good (pgood) output is forced low. the device provides over-voltage-protection: when the voltage sensed on fb pin reaches a value 20% (typ.) greater than the reference, the low-side driver is turned on as long as the over voltage is detected (see figure 10. ). it must be taken into account that there is an electrical network between the output terminal and the fb pin and therefore the voltage at the pin is not a perfect replica of the output voltage. however due to the fact that the converter can sink current, in the most of cases the low-side will turn-on before the output voltage exceeds t he over-voltage threshol d, because the error amplifier will throw off balance in advance. even if the device doesn't repo rt an over-voltage, the behavior is the same, because the low-side is turned-on immediately. the following figure shows the device behavior during an over-voltage event. the output voltage rises with a slope of 100mv/s, emulating in this way the breaking of the high-side mosfet as an over-voltage cause. figure 10. ovp lgate fb
L6732 device description 17/33 the device realizes the over-current-protection (ocp) sensing the current both on the high-side mosfet(s) and the low-side mosfet(s) and so 2 current limit thresholds can be set (see och pin and ocl pin in table 3. pins function): peak current limit valley current limit the peak current protection is active when the high-side mosfet(s) is turned on, after a masking time of about 100ns. the valley-current-protection is enabled when the low-side mosfet(s) is turned on after a masking time of about 400ns. if, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-pr otection) the device enters in hiccup mode: the high-side and low-side mosfet(s) are turned off, the soft-start capacitor is discharged with a constant current of 10a and when the voltage at the ss pin reaches 0.5v the soft-start phase restarts. during the soft-start phase the ocp provides a constant-current-protection. if during the t on the och comparator triggers an over current the high-side mosfet(s) is immediately turned off (after the masking time and the internal delay) and returned on at the next pwm cycle. the limit of this protection is that the t on can't be less than masking time plus propagation delay because during the masking time the peak-current-protection is disabled. in case of very hard short circuit, even with this short t on , the current could escalate. the valley-current-protection is very helpful in this case to limit the current. if during the off-time the ocl comparator triggers an over current, the high-side mosfet(s) is not turned on until the current is over the valley- current-limit. this implie s that, if it is necessary, some pulses of the high-side mosfet(s) will be skipped, guaranteeing a maximum current due to the following formula: in constant current protection a current control loop limits the value of the error amplifier output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. figure 12. shows the behaviour of the device during an over current condition that persists also in the soft-start phase. figure 11. ovp: the low-side mosfet is turned-on in advance. v out v fb lgate 109% min on valley max t l vout vin i i , ? ? + = (4)
device description L6732 18/33 5.9 hiccup mode during an ocp 5.10 thermal shutdown when the junction temperature reaches 150c 10c the device enters in thermal shutdown. both mosfets are turned off and the soft-start c apacitor is rapidly discharged with an internal switch. the device doesn't restart until the junction temperature goes down to 120c and, in any case, until the voltage at the soft-start pin reaches 500mv. 5.11 synchronization the presence of many converters on the same board can generate beating frequency noise. to avoid this it is important to make them operate at the same switching frequency. moreover, a phase shift between different modules helps to minimize the rms current on the common input capacitors. figure 13. and figure 14. shows the results of two modules in synchronization. two or more devices can be synchronized simply co nnecting together the synch pins. the device with the higher switching frequen cy will be the master while the other one will be the slave. the slave controller will increase its switching frequen cy reducing the ramp am plitude proportionally and then the modulator gain will be increased. figure 12. constant current and hiccup mode during an ocp. vss vcomp i l
L6732 device description 19/33 to avoid a huge variation of the modulator gain, the best way to synchronize two or more devices is to make them work at the same switching frequency and, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. if, during synchronization between two (or more) L6732, it's important to know in advance which the master is, it's timely to set its switching frequency at least 15% higher than the slave. using an external clock signal (f ext ) to synchronize one or more devices that are working at a different switching frequency (f sw ) it is recommended to follow the below formula: the phase shift between master and slaves is approximately 180. figure 13. synchronization: pwm signal figure 14. synchronization: inductor currents sw ext sw f f f ? 3 , 1
device description L6732 20/33 5.12 minimum on-time (t on , min ) the device can manage minimum on-times lower than 100ns. this feature comes down from the control topology and from the particular over-current-protection system of the L6732. in fact, in a voltage mode controller the current has not to be sensed to perform the regulation and, in the case of L6732, neither for the over-current protection, given that during the off-time the valley-current-protection can operate in every case. the first advantage related to this feature is the possibility to realize ex tremely low conversion ratios. figure 15. shows a conversion from 14v to 0.3v at 500khz with a t on of about 50ns. the on-time is limited by the turn-on and turn-off times of the mosfets. figure 15. 14v -> 0.3v@500khz, 5a 50ns vphase i l v out
L6732 device description 21/33 5.13 bootstrap anti-discharging system this built-in system avoids that the voltage ac ross the bootstrap capacitor becomes less than 3.3v. an internal comparator senses the voltage across the external bootstrap capacitor keeping it charged, eventually turning-on the low-side mosfet for approximately 200ns. if the bootstrap capacitor is not enough charged the high-side mosfet cannot be effectively turned- on and it will present a higher r dson . in some cases the ocp ca n be also triggered. the bootstrap capacitor can be discharged during the soft- start in case of very long soft-start time and light loads. it's also possible to mention one application condition during which the bootstrap capacitor can be discharged: 5.13.1 fan's power supply in many applications the fan is a dc motor driven by a voltage-mode dc/dc converter. often only the speed of the motor is controlled by varying the voltage applied to the input terminal and there's no control on the torque because the current is not directly controlled. in order to vary the motor speed the output voltage of the converter must be varied. the L6732 has a dedicated pin called earef (see the related section) that allows providing an external reference to the non-inverting input of the error-amplifier. in these applications the duty cycle depends on the motor's speed and sometimes 100% has to be set in order to go at the maximum speed. unfortunately in these conditions the bootstrap capacitor can not be recharged and the system cannot work properly. some pwm controller limits the maximum duty-cycle to 80-90% in order to keep the bootstrap cap charged but this make worse the performance during the load tr ansient. thanks to the "bootstrap anti- discharging system" the L6732 can work at 100% without any problem. the following picture shows the device behaviour when input voltage is 5v and 100% is set by the external reference. figure 16. 100% duty cycle operation
application details L6732 22/33 6 application details 6.1 inductor design the inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ( ? i l ) between 20% and 30% of the maximum output current. the inductance value can be calculated with the following relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 17. shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5v and v in = 12v at a switching frequency of 500khz. increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. if the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. when one of these conditions is reached, the re sponse time is limited by the time required to change the inductor current. during this time the output current is supplied by the output capacitors. minimizing the response time can minimize the output capacitor size. figure 17. inductor current ripple. vin vout i fsw vout vin l l ? ? ? ? ? 0 1 2 3 4 5 6 7 8 01234 output voltage (v) inductor current rippl v in = 5 v , l=500nh v in = 5 v , l = 1 .5 u h v in = 1 2 v , l = 2 u h v in = 1 2 v , l = 1 u h (6)
L6732 application details 23/33 6.2 output capacitors the output capacitors are basic components for the fast transient response of the power supply. they depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. during a load transient, the output capacitors supply the current to the load or absorb the current stored in the inductor until the converter reacts. in fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. the output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the esl): moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas: formula (8) is valid in case of positive load tr ansient while the formula (9 ) is valid in case of negative load transient. d max is the maximum duty cycle value that in the L6732 is 100%. for a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum esr and a minimum c out value can be set. the esr and c out values also affect the static output voltage ripple. in the worst case the output voltage ripple can be calculated with the following formula: usually the voltage drop due to the esr is the biggest one while the drop due to the capacitor discharge is almost negligible. 6.3 input capacitors the input capacitors have to sustain the rms current flowing through them, that is: where d is the duty cycle. the equation reaches its maximum value, i out /2 with d = 0.5. the losses in worst case are: esr iout vout esr ? ? = ? ) max min , ( 2 2 vout d vin cout l iout vout cout ? ? ? ? ? ? = ? vout cout l iout vout cout ? ? ? ? = ? 2 2 ) 8 1 ( fsw cout esr i vout l ? ? + ? ? = ? ) 1 ( d d iout irms ? ? ? = 2 ) 5 . 0 ( iout esr p ? ? = (7) (8) (9) (10) (11) (12)
application details L6732 24/33 6.4 compensation network the loop is based on a voltage mode control ( figure 18. ). the output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. the error amplifier output v comp is then compared with the oscillator triangular wave to provide a pulse- width modulated (pwm) with an amplitude of v in at the phase node. this waveform is filtered by the output filter. the modulator transfer function is the small signal transfer function of v out / v comp . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at fesr depending on the output capacitor's esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-p eak oscillator voltage: v osc . the compensation network consists in the internal error amplifier, the impedance networks z in (r3, r4 and c20) and z fb (r5, c18 and c19). the compensation network has to provide a closed loop transfer function with the highest 0db crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in dc conditions to minimize the load regulation error. a stable control loop has a gain crossing the 0db axis with -20db/decade slope and a phase margin greater than 45. to locate poles and zeroes of the compensation networks, the following suggestions may be used: modulator singularity frequencies: compensation network singularity frequencies: figure 18. compensation network cout l lc ? = 1 cout esr esr ? = 1 (13) (14) ? ? ? ? ? ? ? ? + ? ? = 19 18 19 18 5 1 1 c c c c r p 20 4 2 1 c r p ? = (15) (16) 19 5 1 1 c r z ? = () 4 3 20 2 1 r r c z + ? = (17) (18)
L6732 application details 25/33 compensation network design: ? put the gain r 5 /r 3 in order to obtain the desired converter bandwidth ? place z1 before the output filter resonance lc ; ? place z2 at the output filter resonance lc ; ? place p1 at the output capacitor esr zero esr ; ? place p2 at one half of the switching frequency; ? check the loop gain considering the error amplifier open loop gain. figure 19. asymptotic bode plot of converter's open loop gain lc c vosc vin r r ? ? ? ? ? = 3 5 (19)
L6732 demoboard L6732 26/33 7 L6732 demoboard 7.1 description L6732 demoboard realizes in a four layer pcb a step-down dc/dc converter and shows the operation of the device in a general purpose application. the input voltage can range from 4.5v to 14v and the output voltage is at 3.3v. the module can deliver an output current in excess of 20a. the switching frequency is set at 250 khz (controller free-running f sw ) but it can be set to 500khz acting on the earef pin. figure 20. demoboard schematic table 6. demoboard part list reference value manufacturer package supplier r1 1k ? neohm smd 0603 ifarcad r2 1k ? neohm smd 0603 ifarcad r3 4k7 r4 2k7 neohm smd 0603 ifarcad r5 0 ? neohm smd 0603 ifarcad r6 n.c. neohm smd 0603 ifarcad r7 2k neohm smd 0603 ifarcad r8 10 ? neohm smd 0603 ifarcad r9 1k5 neohm smd 0603 ifarcad r10 2.2 ? neohm smd 0603 ifarcad r11 2.2 ? neohm smd 0603 ifarcad
L6732 L6732 demoboard 27/33 r12 n.c. neohm smd 0603 ifarcad r13 10k ? neohm smd 0603 ifarcad c1 4.7nf kemet smd 0603 ifarcad c2 47nf kemet smd 0603 ifarcad c3 1nf kemet smd 0603 ifarcad c4 100nf kemet smd 0603 ifarcad c5 100nf kemet smd 0603 ifarcad c6 n.c. / / / c7 100nf kemet smd 0603 ifarcad c8 4.7uf 20v avx sma6032 ifarcad c9 1nf kemet smd 0603 ifarcad c10 1uf kemet smd 0603 ifarcad c11 220nf kemet smd 0603 ifarcad c12-13 3x 15uf / / st (tdk) c15 n.c. / / / c16-19 2x 330uf / / st (poscap) l1 1.8uh panasonic smd st d1 stps1l30m st do216aa st d3 stps1l30m st do216aa st q1-q2 sts12nh3ll st so8 st q4-q5 sts25nh3ll st so8 st u1 L6732 st htssop16 st table 7. other inductor manufacturer manufacturer series inductor va lue (h) saturation current (a) wurth elektronic 744318180 1.8 20 sumida cdep134-2r7mc-h 2.7 15 epcos hpi_13 t640 1.4 22 tdk spm12550t-1r0m220 1 22 toko fda1254 2.2 14 coiltronics hcf1305-1r0 1.15 22 hc5-1r0 1.3 27 table 6. demoboard part list
L6732 demoboard L6732 28/33 table 8. other capacitor manufacturer manufacturer series capacitor value(f) rated voltage (v) tdk c4532x5r1e156m 15 25 c3225x5r0j107m 100 6.3 nippon chemi-con 25ps100mj12 100 25 panasonic ecj4yb0j107m 100 6.3 figure 21. demoboard efficiency figure 22. pcb layout: top layer figure 23. pcb layout: power ground layer fsw =400khz 75.00% 80.00% 85.00% 90.00% 95.00% 13579111315 iout (a) efficien
L6732 L6732 demoboard 29/33 figure 24. pcb layout: signal-ground layer figure 25. pcb layout: bottom layer
package mechanical data L6732 30/33 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
L6732 package mechanical data 31/33 table 9. htssop16 mechanical data figure 26. package dimensions dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.15 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 d1 1.7 0.067 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.5 0.169 0.173 0.177 e2 1.5 0.059 e 0.65 0.0256 k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 7419276a
revision history L6732 32/33 9 revision history table 10. revision history date revision changes 20-dec-2005 1 initial release. 24-jan-2006 2 few updates 29-may-2006 3 new template, thermal data updated 26-jun-2006 4 note page 10 deleted
L6732 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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